The flip flop is a basic building block of sequential logic circuits. It is a circuit that has two stable states and can store one bit of state information. The output changes state by signals applied to one or more control inputs.
The basic D Flip Flop has a D (data) input and a clock input and outputs Q and Q (the inverse of Q). Optionally it may also include the PR (Preset) and CLR (Clear) control inputs.
The truth table and diagram
The clock input is usually drawn with a triangular input. This flip-flop is a positive edge-triggered flip flop. This means that the flip flop changes output value only when the clock is at a positive edge (or rising clock edge). There is also a negative edge triggered flip flop, which changes on a negative clock edge (or falling clock edge).
Divide-by-4 Ripple Counter - By connecting D to Q, we obtain a divide by 2 counter. The frequency at the output Q compared to the input clock CLK frequency is divided by two. Using 2 flip flops, a divide-by-4 ripple counter is obtained. By cascading n flip flops, we get a divide by 2n counter.
Ring Counter - A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the last flip flop connected to the input of the first.
Johnson Counter - A Johnson counter is a modified ring counter, where the inverted output from the last flip flop is connected to the input to the first.
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