The flip flop is a basic building block of sequential logic circuits. It is a circuit that has two stable states and can store one bit of state information. The output changes state by signals applied to one or more control inputs.
The basic JK Flip Flop has J,K inputs and a clock input and outputs Q and Q (the inverse of Q). Optionally it may also include the PR (Preset) and CLR (Clear) control inputs.
The truth table and diagram
The clock input is usually drawn with a triangular input. This flip-flop is a negative edge-triggered flip flop. This means that the flip flop changes output value only when the clock is at a negative edge (or falling clock edge).
By connecting the CLK input of the second JK flip flop to Q of the first JK FF, we obtain a 2 bit Up Counter. The output is at both Q of the flip flops. The count sequence for Q1Q0 is 00,01,10,11,00,01 ... where Q1 is the MSB (Most Significant Bit) and Q0 (Least Significant Bit) is the LSB.
On the other hand, connecting CLK to Q, we obtain a 2 bit Down Counter. The count sequence for Q1Q0 is 00,11,10,01,00,11 ...
When J and K are connected to 1, the JK flip flop is in the toggle mode. By applying low and then high to CLR clears the Q0 and Q1 outputs to 0. By cascading n flip flops, we get a count to 2n counter.
The natural count sequence is to run through all possible combinations of the bit patterns before repeating itself. A Truncated Ripple Counter uses external logic to cause the counter to terminate at a specific count. A decade counter counts from 0 to 9.