Combinational Arithmetic Circuits are circuits that perform arithmetic functions like Addition, Subtraction and Multiplication. They are structured or array combinational circuits. For example, an n-bit adder is made up of a 1-dimensional array of 1-bit full adders.

From binary addition, we learn that the

- 0+0 = 0, with no carry,
- 0+1 = 1, with no carry,
- 1+0 = 1, with no carry,
- 1+1 = 0, and carry 1

From these rules, we obtain the truth table for the half adder

Implementation of the half adder using combinational logic circuits.

Learning by Doing

Learn to Design a Half Adder in minutes to understand the circuit better.

From binary addition, we also learn that the half adder only works on the Least Significant Bit (LSB) of the binary number. For all higher bits, we have to consider the carry in bit. Thus the new rules are

- when result = 0
_{2}, carry = 0 sum = 0 - when result = 1
_{2}, carry = 0 sum = 1 - when result = 10
_{2}, carry = 1 sum = 0 - when result = 11
_{2}, carry = 1 sum = 1

From these rules, we obtain the truth table for the full adder

We implement the full adder using two of the half adders described earlier. Click on the half adder sub circuit to see its implementation.

Learning by Doing

Learn to Design a Full Adder in minutes to understand the circuit better.

Using structured or array combinational circuits, we can construct a 2-bit adder using a half adder for the LSB and one 1-bit full adder. Change the inputs A1,A0 (A0 is LSB) and B1,B0 (B0 is LSB) and observe the output results D2-D0 (D0 is LSB) that it is indeed **D = A + B**.

From binary addition using 2's complement, we learnt that

- D = A - B = A + (-B)
- -B can be represented by 2's complement. To obtain the 2's complement, first we invert the bits of B and then add 1.
- In our implementation, we modify a 2 bit adder using two 1 bit full adders. To obtain the 2's complement, the inputs of B are inverted and the carry-in of the LSB is set to 1 to perform the add 1.
- For 2 bits and using 2's complement representation, the range of input values is limited from -2 (-2
^{2-1}) to 1 (2^{2-1}-1). - The output is also in the 2's complement format.

Change the inputs A1,A0 (A0 is LSB) and B1,B0 (B0 is LSB) and observe the output results D1,D0 (D0 is LSB) that it is indeed **D = A - B**.

Note that C = 1. The allowed values for A are 0,1 and the B allowed values are 0,1,10_{2}. The D results are in 2's complement format.

Modify the circuit to obtain a 3 bit subtractor.

This is the schematic of a 3 bit adder. Change the inputs to observe the circuit operation **D = A + B**. A0, B0 , D0 are the Least Significant Bits (LSB).

Modify the circuit to obtain a 4 bit adder.

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