# SR NOR latch

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.

The truth table and diagram

The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output 0s, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values

### Notes

• The green switch is a on/off switch (similar to a room light switch).
• Q0 is the previous state of Q and Q0 is the previous state of Q.
• R and S are asynchronous inputs - that is the output responds to these input immediately. They are active high inputs. Click on their respective green switches and observe.
• S sets the output to 1 and R resets the output to 0.
• Both R and S cannot be high at the same time - the output is undefined.
• Simulate and Breadboard the SR NOR circuit.
• Watch the video to learn how to edit the input (thick) waveforms.