Successive approximation register ADC

Successive approximation register (SAR) analog to digital converters (ADCs) are frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 megasamples per second (Msps). Resolution for SAR ADCs most commonly ranges from 8 to 16 bits, and they provide low power consumption as well as a small form factor. The SAR ADC basically implements a binary search algorithm.

High Low Game

One way is understand the binary search algorithm is to recall how to play the high low game. You are asked to guess a secret number say between 0 to 15. At every guess, you will be told whether your guess is higher or lower than the secret number.

One efficient method is to half the number in the correct range. Lets do it with an example, assume the secret number is 11

  1. A number between 0-15. Guess half of range -> 810 or 10002.
    Is Secret>Guess (11>8)? True
  2. A number between 9-15. Guess half of range -> 1210 or 11002.
    Is Secret>Guess (11>12)? False
  3. A number between 9-11. Guess half of range -> 1010 or 10102.
    Is Secret>Guess (11>10)? True
  4. Guess 1110 or 10112

You will notice that we have shown the guess both in decimal and binary form. The reason is that in the binary form you can see the pattern in which we select the guess.

  1. Set the MSB to 1 (1000)
    • if Secret>Guess then bit remains 1
    • if Secret<Guess then bit set to 0
    From the above example, Secret>Guess is true, then MSB remains 1 (1000).
  2. Then the next bit is set to 1 (1100). Since Secret<Guess then this bit is set to 0 (1000)
  3. Set the next bit to 1 (1010). The algorithm is repeated until LSB is tested.

Binary search algorithm

  • Initially, DAC input set to midscale (MSB = 1 or D3 = 1)
    • if Vin > Vo (DAC voltage output), D3 remains 1
    • if Vin < Vo, D3 set to 0
  • Then the next bit (D2) is set to 1 and the algorithm is repeated until LSB (D0)
  • At the end of algorithm, ADC output is the DAC input
  • N (4) cycles required for N-bit (4-bit) conversion

Notes:

  • Circuit shown is a 4 bit SAR ADC.
  • To observe the operation of the SAR ADC, first set the Vin
  • Press the START button to begin the binary search process
  • U5 samples and holds the Vin voltage to V+ of the the comparator (U1) when the START button is pressed. V+ does not change during the conversion process.
  • Press the CLK button to observe the results of each cycle of the binary search algorithm.
  • U3 is a 4 bit DAC with step voltage of 0.25V
  • EOC LED lights up when the conversion is complete.
  • To repeat the process with a different input voltage, press the START button again.