# BJT Common Emitter Amplifier with emitter degeneration

A basic BJT common emitter amplifier has a very high gain that may vary widely from one transistor to the next. The gain is a strong function of both temperature and bias current, and so the actual gain is somewhat unpredictable. One common way of alleviating these issues is with the use of emitter degeneration. Emitter degeneration refers to the addition of a small resistor (R4) between the emitter and the common signal source.

In this circuit the base terminal of the transistor is the input, the collector is the output, and the emitter is common to both. It is a voltage amplifier with an inverted output. The common emitter bjt amplifier is one of three basic single-stage bipolar-junction-transistor (BJT) amplifier configurations.

Notes:
• Measure the simulated results and compare with the theoretical ones by using the formulae derived below. You can obtain the waveform values by clicking within the graph. Assume the following for your calculations
• VBE = 0.7V
• β = 100
• We are using the 2N3904 transistor model. If you construct this circuit in the laboratory correctly using the 2N3904 transistor, you should see similar results.
• Use the Toggle Plot to see the graphs combined or stacked. The stacked plots display maximised waveforms whereas the combined waveforms show their relative values.
• When you choose capacitor CE to be 10nF, its reactance (@ signal source frequency 1KHz) is much smaller than R4 and can be ignored. Redraw the AC equivalent circuit without CE and derive the voltage gain. $${v_c \over v_i} = -{R_3 \over r_e + R_4}$$

## DC Analysis

First we redraw the schematic using the BJT DC model. Capacitors are considered open circuit in DC and therefore are excluded.

IB can be ignored if $$10R_2 < \beta R_4$$ Thus VB can be calculated using KVL as simple voltage divider circuit $$V_B = {R_2 \over {R_1 + R_2}} V_S$$ Current at Node E $$I_E = I_B + I_C$$ if IC is much greater than IB, IB can be ignored $$I_E = I_C$$

Using KVL (Kirchhoff's voltage law) $$V_B = I_ER_4 + V_{BE}$$ $$V_S = I_CR_3 + V_{C}$$

If you are designing rather than analysing the DC circuit, you should choose the resistor values such that VC is half the supply voltage. This is to obtain maximum output voltage swing.

$$V_{C} = {V_S \over 2}$$

## AC Analysis

Next we redraw the schematic using the BJT small signal model. Capacitors are considered shorts in AC (R4 is shorted out by Ce) and DC supplies are connected to GND (ground). Calculate re

$$r_e = {v_T \over I_E}$$

Since the input voltage vi is across re and using ohm's law

$$i_e = {v_i \over r_e}$$

The output voltage is $$v_c = -i_cR_3$$ the inverted output is due to the current direction.

From KCL we know that $$i_e = i_b + i_c$$ By ignoring ib from the equation since it is small compared to ic, we obtain $$v_c = -i_eR_3$$

Applying equation 9 to equation 12, the voltage gain of the amplifier is $${v_c \over v_i} = -{R_3 \over r_e}$$